| 主权项 |
1. A clock generating circuit, comprising:
a counter that counts a number of pulses of an oscillation clock signal existed within one cycle of a reference clock signal; a first time-to-digital converter that generates a plurality of phases of first clock signals by relatively delaying the oscillation clock signal with respect to the reference clock signal using a plurality of first delay elements, and outputs values of the plurality of phases of first clock signals at an edge point of the reference clock signal as a first digital value; a second time-to-digital converter that generates a plurality of phases of second clock signals by relatively delaying the oscillation clock signal with respect to the reference clock signal using a plurality of second delay elements each having a delay time shorter than a delay time of each of the first delay elements, and outputs values of the plurality of phases of second clock signals at the edge point of the reference clock signal as a second digital value; a third time-to-digital converter that generates a plurality of phases of third clock signals by relatively delaying the first clock signal delayed by the plurality of first delay elements with respect to the reference clock signal using a plurality of third delay elements each having a delay time which is the same as the delay time of each of the second delay elements, and outputs values of the plurality of phases of third clock signals at the edge point of the reference clock signal as a third digital value; a delay control unit that outputs a delay control signal based on a difference between a cycle of the oscillation clock signal obtained based on at least the first digital value and the third digital value and a target cycle; and an oscillator that generates, based on a cycle of the reference clock signal obtained based on a count number of the counter and the first to third digital values, the oscillation clock signal whose cycle is 1/m (m is an integer of 2 or more) of the cycle of the reference clock signal, wherein: the delay time of each of the plurality of first delay elements in the first time-to-digital converter is changed in accordance with the delay control signal output by the delay control unit; and the first time-to-digital converter outputs the plurality of phases of first clock signals. |
