发明名称 Method and apparatus for processing latency sensitive electronic data with interrupt moderation
摘要 Numerous embodiments of a method and apparatus for processing latency sensitive electronic data with interrupt moderation are disclosed.
申请公布号 US8856416(B2) 申请公布日期 2014.10.07
申请号 US200110007082 申请日期 2001.12.06
申请人 Intel Corporation 发明人 Minnick Linden;Connor Patrick L.
分类号 G06F13/24;H04L12/861;H04L29/06 主分类号 G06F13/24
代理机构 代理人 Gagne Christopher K.
主权项 1. An apparatus comprising: an input/output (I/O) device to determine whether to defer interrupting of a processor to process a received fragment of electronic data, based at least in part upon both a priority of the received fragment and a number of interrupts generated per unit of time, the device to determine whether to defer the interrupting such that if the priority of the received fragment is a relatively higher priority relative to a relatively lower priority and the number of interrupts generated per the unit of time exceeds a predetermined maximum number, the device is to determine that the interrupting for the received fragment of the relatively higher priority is to be deferred for a particular time period, even though the received fragment is of the relatively higher priority; a graphical user interface to permit user entry of device programmable criteria, the device programmable criteria being to program the device to interupt the processor based upon the criteria, the criteria comprising an elapsed time after receipt of the received fragment and quantity of received fragments of the electronic data; wherein: the device comprises memory to store fragments of the electronic data designated for a streaming media application;the device is to defer the interrupting until after a certain amount of the memory has been utilized to store the fragments; andthe received fragment comprises a transmission control protocol (TCP) acknowledgement (ACK) packet.
地址 Santa Clara CA US