发明名称 |
Nonvolatile semiconductor memory device |
摘要 |
A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings, a voltage generating circuit configured to generate control voltages of different voltage levels, and a control circuit configured to control application of control voltages to the word lines and the back gate line. A control voltage applied to the back gate line may be varied depending on how far a selected word line is from the back gate line, and a control voltage applied to unselected word lines may be varied depending on how far the unselected word line is from the selected word line. |
申请公布号 |
US8854896(B2) |
申请公布日期 |
2014.10.07 |
申请号 |
US201313785666 |
申请日期 |
2013.03.05 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Hosono Koji;Shano Toshifumi |
分类号 |
G11C8/08;G11C16/30;G11C16/08;G11C16/26;G11C11/4074;G11C5/14;G11C16/24;G11C16/04;G11C7/00 |
主分类号 |
G11C8/08 |
代理机构 |
Patterson & Sheridan, LLP |
代理人 |
Patterson & Sheridan, LLP |
主权项 |
1. A nonvolatile semiconductor memory device, comprising:
multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of serially connected memory cells; a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings; a back gate line connected to the control gates of the back gate transistors; and a voltage generating circuit configured to generate first, second, and third control voltages of different voltage levels, the first voltage having a higher voltage level than the second control voltage and the second control voltage having a higher voltage level than the third control voltage; and a control circuit configured to control application of control voltages to the word lines and the back gate line, wherein when a word line connected to the control gates of the memory cells in the first and second groups that are adjacent to the back gate transistor is a selected word line, the first control voltage is applied to the selected word line and the second control voltage is applied to the back gate line, and when a word line connected to the control gates of the memory cells in the first and second groups that are that are not adjacent to the back gate transistor is a selected word line, the first control voltage is applied to the selected word line and a control voltage that is less than or equal to the third control voltage is applied to the back gate line. |
地址 |
Tokyo JP |