发明名称 REDUCING RUNTIME AND MEMORY REQUIREMENTS OF STATIC TIMING ANALYSIS
摘要 Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis.
申请公布号 US2014298280(A1) 申请公布日期 2014.10.02
申请号 US201313855226 申请日期 2013.04.02
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 DREIBELBIS Brian;DUBUQUE John P.;FOREMAN Eric A.;HATHAWAY David J.;HEMMETT Jeffrey G.;VENKATESWARAN Natesan;VISWESWARIAH Chandramouli;ZOLOTOV Vladimir
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method comprising: obtaining canonical input data; calculating at least one input condition identifier based on the canonical input data; comparing the at least one input condition identifier to a table of values; and when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis; and when a match does not exist between the at least one input condition identifier and the at least one value within the table of values, calculating timing data for the at least one input condition identifier, saving the at least one input condition identifier as a value in the table of values, and applying the calculated timing data for the at least one input condition identifier in the timing model for the design under timing analysis, wherein at least the comparing is performed using a processor.
地址 Armonk NY US