SINGLE-LAYER GATE EEPROM CELL, CELL ARRAY INCLUDING THE SAME, AND METHOD OF OPERATING THE CELL ARRAY

摘要

A cell array portion of a single-layer gate EEPROM device includes a plurality of unit cells formed over a substrate to share a first well region in the substrate. Each of the plurality of unit cells includes a floating gate having a first part disposed over the first well region and a second part extending from the first part to have a strip shape, a selection gate spaced apart from the floating gate and disposed to be parallel with the second part of the floating gate, and an active region disposed in the substrate to intersect the floating gate and the selection gate.

主权项

1. A cell array of a single-layer gate electrically erasable programmable read-only memory (EEPROM) device, the cell array comprising:
a substrate; and a plurality of unit cells sharing a first well region in the substrate, wherein each of the plurality of unit cells comprises:
a floating gate including a first part disposed over the first well region and a second part extending from the first part in a first direction, the second part having a strip shape and disposed over a second well region different from the first well region;a selection gate spaced apart from the floating gate and disposed over the second well region and parallel with the second part of the floating gate; andan active region disposed in the substrate and parallel with a second direction substantially perpendicular to the first direction, the active region intersecting the floating gate and the selection gate,wherein the active region includes a first impurity region disposed at one side of the second part of the floating gate, a second impurity region disposed at one side of the selection gate, and a third impurity region disposed at the respective other sides of the selection gate and the second part of the floating gate.