UNCORE MICROCODE ROM

摘要

A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions.

主权项

1. A microprocessor, comprising:
a plurality of processing cores, wherein each core of the plurality of processing cores comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other of the plurality of processing cores (hereinafter “core memory”); a memory physically located outside all of the plurality of processing cores and readable by all of the plurality of processing cores (hereinafter “uncore memory”); wherein, for each core of the cores, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows:
the uncore memory provides J of the M words of microcode instruction storage; andthe corresponding core memory provides K of the M words of microcode instruction storage, wherein J, K and M are counting numbers, wherein M=J+K.