发明名称 |
LATCH CIRCUIT, SCAN TEST CIRCUIT AND LATCH CIRCUIT CONTROL METHOD |
摘要 |
A latch circuit includes: a data latch that holds data that has been input according to a first control signal or a second control signal; and a latch controller that includes a first input terminal to which a first operation signal is input, the first operation signal operating the data latch in a first scan method, and a second input terminal to which a second operation signal is input, the second operation signal operating the data latch in a second scan method; wherein when a prescribed value is input to the first input terminal, the latch controller outputs the second control signal to control the data latch, and when a prescribed value is input to the second input terminal, the latch controller outputs the first control signal to control the data latch. |
申请公布号 |
US2014298126(A1) |
申请公布日期 |
2014.10.02 |
申请号 |
US201414225620 |
申请日期 |
2014.03.26 |
申请人 |
FUJITSU LIMITED |
发明人 |
Sugiyama Itsumi |
分类号 |
H03K3/0233;G01R31/3177 |
主分类号 |
H03K3/0233 |
代理机构 |
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代理人 |
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主权项 |
1. A latch circuit, comprising:
a data latch that holds data that has been input according to one of a first control signal and a second control signal; and a latch controller that comprises:
a first input terminal to which a first operation signal is input, the first operation signal operating the data latch in a first scan method, anda second input terminal to which a second operation signal is input, the second operation signal operating the data latch in a second scan method; wherein
when a prescribed value is input to the first input terminal and the second operation signal is input to the second input terminal, the latch controller outputs the second control signal to control the data latch, andwhen a prescribed value is input to the second input terminal and the first operation signal is input to the first input terminal, the latch controller outputs the first control signal to control the data latch. |
地址 |
Kawasaki-shi JP |