Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system

摘要

Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.

主权项

1. A memory system comprising:
a first memory array comprising a plurality of first memory cells,
each first memory cell being identical in design and requiring a corresponding time delay between wordline activating and bitline sensing during a read operation, andsaid plurality of first memory cells requiring a range of different corresponding time delays between said wordline activating and said bitline sensing from long time delays corresponding to slow memory cells to short time delays corresponding to fast memory cells, said range of different corresponding time delays being required due to different performance characteristics of said memory cells and said different performance characteristics being caused by at least one of process variations, temperature variations and voltage variations; and a delay signal generator receiving an input signal and delaying said input signal by a selected time delay within said long time delays so as to generate and output a delay signal that ensures functionality of at least some of said slow memory cells during said read operation.