发明名称 |
Integrated circuit for signal analysis |
摘要 |
An integrated circuit comprises a main bus, one or more integrated processors, an external bus interface, memory, internal bus controller, a signal analyzer, timers, reset/clock generator, radio controller, optional data converters, and optional radio. The signal analyzer performs both time-domain and frequency-domain analysis of the input signal and supplies data to the one or more integrated processors for signal classification. |
申请公布号 |
US8849213(B2) |
申请公布日期 |
2014.09.30 |
申请号 |
US200912623598 |
申请日期 |
2009.11.23 |
申请人 |
Bandspeed, Inc. |
发明人 |
Jones Ben William;Mammoser Douglas A.;Morton John M.;Bagge Nils;Bhulani Bhavin;Wingert Matthew P.;Killian Harrison J. |
分类号 |
H04B17/00 |
主分类号 |
H04B17/00 |
代理机构 |
Hickman Palermo Truong Becker Bingham Wong LLP |
代理人 |
Hickman Palermo Truong Becker Bingham Wong LLP ;Becker Edward A. |
主权项 |
1. An integrated circuit, comprising:
a bus; one or more integrated processors connected to the bus; and a signal analyzer connected to the bus, the signal analyzer including a time-domain analyzer that provides time-domain data that indicates time-domain characteristics of signals and a frequency-domain analyzer that provides frequency-domain data that indicates frequency-domain characteristics of the signals, wherein the one or more integrated processors cause adaptive scanning to be performed on two or more communications channels based upon at least the time-domain data provided by the time-domain analyzer and the frequency-domain data provided by the frequency-domain analyzer, wherein the adaptive scanning includes one or more of increasing a dwell time for at least one communications channel from the two or more communications channels or changing a scanning sequence for the two or more communications channels. |
地址 |
Austin TX US |