Latch-based array with robust design-for-test (DFT) features

摘要

A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.

主权项

1. A latch-based memory, comprising:
a plurality of slave latches arranged into a plurality of rows, each row being configured to be clocked by a corresponding row write clock; a plurality of row clock gating circuits corresponding to the plurality of rows, each row clock gating circuit (row CGC) being configured to gate the corresponding row write clock for its row responsive to its row being inactive for a write operation by holding the corresponding row write clock in a first clock state; and a plurality of row reset circuits corresponding to the plurality of rows, each row reset circuit configured to reset the corresponding row write clock for its row responsive to an assertion of a reset signal by holding the corresponding row write clock in a second clock state.