Self-calibration of output buffer driving strength

摘要

An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

主权项

1. An integrated circuit comprising:
a buffer circuit having a signal input, a signal output, and a set of control inputs, the buffer circuit having a driving strength adjustable in response to control signals applied to the set of control inputs; and a control circuit connected to the set of control inputs of the buffer circuit, the control circuit using first and second timing signals to generate the control signals, and including a reference delay circuit that generates the first timing signal with a reference delay substantially insensitive to at least one of process, voltage and temperature (PVT) conditions, and a delay emulation circuit that generates the second timing signal with an emulation delay that changes with variations in delay of the buffer circuit resulting from said at least one of process, voltage and temperature (PVT) conditions.