| 摘要 |
PROBLEM TO BE SOLVED: To provide processors, methods, and systems to relax synchronization of accesses to a shared memory.SOLUTION: A processor 101 includes memory access synchronization relaxation logic 109. The logic 109 is operable, when appropriate, to relax synchronization of accesses to a shared memory 115. For example, in some embodiments, the logic 109 prevents a memory access synchronization instruction (e.g., one or more of fence/barrier instructions 104, a lock instruction 105, a conditional access instruction 106, etc.) from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode. |
