| 摘要 |
PROBLEM TO BE SOLVED: To make logic verification more efficient and shorten a verification period by correcting a test pattern while continuing a verification simulation of a logic circuit.SOLUTION: A logic verification device comprises: an event table 121 that defines an event occurrence condition consisting of at least one single condition; a condition occurrence table 120 that describes satisfaction method information for increasing occurrence frequency of the single condition; coverage information 110 that stores the number of event occurrences; and a pattern-generation-control change instruction unit 108 that extracts a single condition constituting the occurrence information for the event with a small number of occurrences from the event table 121, extracts the satisfaction method information for the extracted single condition from the occurrence table 120, generates control change instruction information for correcting a test pattern 103 and outputs the generated information to a pattern generation control unit 102. |
