发明名称 Testing Integrated Circuit Packaging for Shorts
摘要 An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more groups of pins such that each pin in each group is not adjacent to a pin from its own group of pins. One of the groups of pins is tested for continuity while placing a reference voltage level on all of the pins in the other groups of pins. A separate current source is coupled to each pin and a resultant voltage is measured. A short between one of the pins in the first group and a pin in one of the other groups can be detected when the resultant voltage on one of the pins in the first group is approximately equal to the reference voltage. Group-wise testing is repeated until all groups have been tested.
申请公布号 US2014285229(A1) 申请公布日期 2014.09.25
申请号 US201313849431 申请日期 2013.03.22
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 Chia Hoon Siong;Ong Chee Peng
分类号 G01R31/30 主分类号 G01R31/30
代理机构 代理人
主权项 1. A method for testing an electronic package having an array of pins for shorts, the method comprising: allocating at least a portion of the array of pins to four or more groups of pins such that each pin in each group is not adjacent to a pin from its own group of pins; testing in parallel all of the pins in a first one of the groups of pins for continuity to a corresponding electrical component within the package while placing a reference voltage level on all of the pins in the other groups of pins, wherein each pin in the first group is tested for continuity by connecting a separate current source to the pin and measuring a resultant voltage on the pin; and determining a short exists between a one of the pins in the first group with a pin in one of the other groups when the resultant voltage on one of the pins in the first group is approximately equal to the reference voltage level.
地址 Dallas TX US