| 摘要 |
PROBLEM TO BE SOLVED: To provide a programmable logic device that implements a lower power consumption while keeping an operating speed intact.SOLUTION: The programmable logic device includes a plurality of programmable logic elements (PLEs) whose electrical connection is controlled by first configuration data. The PLEs each have an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF into which the output signal of the LUT is input, and a MUX. The MUX has at least two switches each having a first transistor, and a second transistor having a gate fed with a signal including third configuration data via the first transistor and either a source or a drain fed with an output signal of the LUT or an output signal of the FF. The others of the sources and drains of the respective second transistors of the at least two switches are electrically connected together. |
