| 摘要 |
Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output. |
| 主权项 |
1. A synchronous memory device, comprising:
memory circuitry having a memory output (Q) and including: a sense amplifier having a first output and a second output;
a first data path (B1) coupled to the first output of the sense amplifier, the first data path having two latches/registers;a second data path (B2) coupled to the second output of the sense amplifier, the second data path having three latches/registers;wherein the first data path and the second data path are utilized in providing a double data rate output; and control circuitry coupled via control lines to the latches/registers in the first and second data paths and including transistors that provide control signals on the control lines to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information; wherein the memory circuitry and control circuitry provide pipelined output latching via circuit configuration, circuit operation and/or a plurality of modes of operation. |
