发明名称 APPARATUS AND METHODS EMPLOYING VARIABLE CLOCK GATING HYSTERESIS FOR A COMMUNICATIONS PORT
摘要 <p>An apparatus includes a communications port configured to communicate over a bus responsive to a clock signal and a clock signal generation circuit configured to generate the clock signal and to vary a gating hysteresis of the clock signal responsive to a control input, such as a communications transaction of the port. The clock signal generation circuit may be configured to vary the gating hysteresis of the clock signal based on an attribute of the transaction, such as an address of the transaction and/or a payload communicated in the transaction.</p>
申请公布号 KR101442791(B1) 申请公布日期 2014.09.24
申请号 KR20127031677 申请日期 2011.04.27
申请人 发明人
分类号 G06F1/04;G06F1/32 主分类号 G06F1/04
代理机构 代理人
主权项
地址