Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks

摘要

An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.

主权项

1. An integrated circuit (IC) comprising:
a digital circuit comprising:
a derived clock circuit configured to receive a root clock having a frequency D*f and a single phase, wherein D is a divide factor for the root clock, wherein the derived clock circuit is configured to divide the root clock by D and generate multiphase clocks having N phases, N and D being positive integers, wherein the multiphase clocks cause a shift in interference signals to have a frequency N*f and harmonics thereof;N circuits configured to receive a corresponding one of the multiphase clocks, wherein edges of the multiphase clocks provided to the N circuits are spread over the N phases, wherein the interference signals having the frequency N*f and harmonics thereof, are generated by a reduced periodic peak current drawn by the N circuits; andan analog circuit configured to receive an in-band range of signals, wherein a value of N is configured to cause the interference signals corresponding to the frequency N*f and harmonics thereof, to be shifted outside the in-band range of signals;wherein the multiphase clocks have the frequency f and the N phases, wherein D=N′P, P being equal to a separation between the N phases;wherein the derived clock circuit further comprises:a Gray counter configured to divide the root clock and generate the multiphase clocks having multiple frequencies, wherein no two bits of the Gray counter toggle at a time.