发明名称 |
Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method |
摘要 |
A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via. |
申请公布号 |
US8841749(B2) |
申请公布日期 |
2014.09.23 |
申请号 |
US201113298823 |
申请日期 |
2011.11.17 |
申请人 |
STMicroelectronics SA;STMicroelectronics (Crolles 2) SAS |
发明人 |
Joblot Sylvain;Farcy Alexy;Carpentier Jean-Francois;Bar Pierre |
分类号 |
H01L21/02;H01L23/58;H01L49/02;H01L23/64;H01L23/48;H01L21/768;H01L23/522 |
主分类号 |
H01L21/02 |
代理机构 |
Gardere Wynne Sewell LLP |
代理人 |
Gardere Wynne Sewell LLP |
主权项 |
1. A semiconductor device comprising:
a wafer having a front face and a rear face and in which is formed a main blind hole in its front face; a capacitor formed in the main blind hole which comprises:
a conductive outer layer covering a side wall and a bottom of the main blind hole and forming an outer electrode,a dielectric intermediate layer covering the conductive outer layer and forming a dielectric membrane, anda filling conductive material, at least partially filling the main blind hole and forming an inner electrode; a secondary rear hole formed in the rear face of the wafer, at least partially revealing a bottom surface of the outer electrode; and a rear electrical connection on the rear face of the wafer and in electrical contact with the bottom surface of the outer electrode through the secondary rear hole. |
地址 |
Montrouge FR |