HARDWARE SIMULATION CONTROLLER, SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION

摘要

Systems and methods of using hardware to simulate software, specifically the semantic operations defined in HDL simulation languages. Traditional software HDL simulation kernel operations of advancing time, activating threads in response to notified events, and scheduling those threads of execution are handled via a simulation controller. The simulation controller is comprised of a timing wheel, an event-processor, a thread/process dispatch engine, a token processor, and a resource-allocator. These components work together with a control logic component to perform the semantic operations of an HDL software kernel.

主权项

1. A logic processor for processing two-state and four-state simulation data, comprising:
an instruction fetch unit configured to retrieve and buffer a plurality of simulation instructions; an instruction decode unit configured to receive and decode instructions from the instruction fetch unit; a four-state register file comprising a plurality of pairs of registers to load data in accordance with the decoded instructions, each register of a pair corresponding to a Verilog data structure; and an arithmetic logic unit configured to use hardware device language semantic arithmetic, logical, and comparison operations on data in the pairs of registers.