| 摘要 |
In one example embodiment, a programmable capacitor array is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry to switch on and off an array of MOSFET switches. The control circuitry turns on a MOSFET to load a capacitance on Vin and turns off the MOSFET to remove the capacitance from Vin in response to a Din control signal. When the intention is to load Vin with the capacitance, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance from Vin, the MOSFET is primarily turned off, however, the MOSFET is still periodically turned on with appropriate voltage levels in response to a clock signal for periods of time when the loading of the capacitance on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system. |
| 主权项 |
1. A low distortion programmable capacitor for minimizing linearity degradation on an input signal, the capacitor being active for a period of time defined by a clock input and comprising:
a Vin input for receiving a Vin signal having voltage values and slew rates in a selected range; a capacitor coupled between the Vin input and a first node; a transistor having a gate, a drain coupled to the first node, a source coupled to a second node at a voltage VS, a backgate terminal coupled to a third node at a voltage VPW, and an internal parasitic PN diode between the first and third nodes, the transistor configured to turn on to load the Vin input with the capacitor and turn off to remove the load of the capacitor from the Vin input in response to a VG signal on the gate; and control circuitry that has a Din input and a clock input, the control circuitry configured to provide the VG signal to turn on the transistor when the Din input is in a first state, and, when the Din input is in a second state, to provide the VG signal to switch the transistor on and off in response to a signal on the clock input, wherein the voltage levels of VS, VPW and VG are selected so that when the VG signal turns the transistor off, the transistor and the internal parasitic PN diode of the transistor remain off throughout the selected range of voltage values and slew rates of Vin. |
