发明名称 PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER AND IN-ORDER MODES
摘要 A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.
申请公布号 US2014281402(A1) 申请公布日期 2014.09.18
申请号 US201313801503 申请日期 2013.03.13
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Comparan Miguel;Hilton Andrew D.;Jacobson Hans M.;Rogers Brian M.;Shearer Robert A.;Vu Ken V.;Watson, III Alfred T.
分类号 G06F9/38 主分类号 G06F9/38
代理机构 代理人
主权项 1. A circuit arrangement, comprising: a hybrid pipeline including a plurality of pipeline stages configured to execute at least one instruction stream, wherein the plurality of pipeline stages includes a dispatch stage, wherein the dispatch stage is configured to dispatch instructions to an issue queue when the hybrid pipeline is in an out-of-order mode, and wherein the dispatch stage is configured to bypass the issue queue when the hybrid pipeline is in an in-order mode; and control logic coupled to the hybrid pipeline and configured to dynamically switch the hybrid pipeline between the out-of-order and in-order modes to selectively execute instructions from the at least one instruction stream using out-of-order and in-order pipeline processing.
地址 Armonk NY US