Delay Timer Device, Method for Managing a Plurality of Delays, and Apparatus for Delaying a Plurality of Data Packets

摘要

An embodiment delay timer for timing a plurality of delays includes a delay clock comprising a number of clock memories, wherein the number of clock memories corresponds to a number of digit positions of a delay clock value, and a delay memory configured to store the plurality of delays. The delay timer further includes a delay logic unit configured to add a new delay by storing it in the delay memory and to time the new delay by coupling it to that clock memory which corresponds to the most significant digit position of the delay value of the new delay that is not zero, by subsequently coupling the new delay to that clock memory which corresponds to the next less significant digit position of the delay value according to the delay value of the new delay and by generating a delay signal when the new delay expires.

主权项

1. A delay timer device for timing a plurality of delays, comprising:
a delay clock comprising a number of clock memories, wherein the number of clock memories corresponds to a number of digit positions of a delay clock value; a delay memory configured to store the plurality of delays; and a delay logic unit configured to add a new delay by storing it in the delay memory and to time the new delay by coupling it to that clock memory which corresponds to a most significant digit position of a delay value of the new delay that is not zero, by subsequently coupling the new delay to that clock memory which corresponds to a next less significant digit position of the delay value of the new delay and by generating a delay signal when the new delay expires.