Methods for Layout Verification for Polysilicon Cell Edge Structures in FinFET Standard Cells

摘要

Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.

主权项

1. A method, comprising:
defining standard cells including at least one transistor and polysilicon dummy structures formed on cell edges; forming a pre-layout schematic netlist from an input gate level netlist using the standard cells, wherein the pre-layout schematic netlist includes a three terminal device corresponding to each of the polysilicon dummy structures; using the gate level netlist, performing an automated place and route process to form a layout netlist for fabricating an integrated circuit using the standard cells; laying out the standard cells and laying out routing connections between the standard cells to form a layout for the integrated circuit, using the layout netlist; extracting from the layout for the integrated circuit a post-layout netlist schematic, the post-layout netlist schematic including a three terminal device for each polysilicon dummy structure in the layout netlist; and comparing the pre-layout netlist to the post-layout netlist.