SHARED BIT LINE STRING ARCHITECTURE

摘要

Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings.

主权项

1. A method for operating a shared bit line string architecture, comprising:
determining that a memory cell is associated with a first string of a pair of strings, the pair of strings includes the first string and a second string, the first string includes a first select transistor with a first threshold voltage, the second string includes a second select transistor with a second threshold voltage different from the first threshold voltage, the first select transistor and the second select transistor are connected to a drain-side select line; setting an SEO transistor into a conducting state, the SEO transistor is connected to the first string and the second string; and performing an operation on the memory cell.