| 摘要 |
The present invention addresses the problem of preventing, in a field-programmable gate array (FPGA) circuit that processes parallelized signals, a reduction in reliability caused by the destruction of circuit configuration information, with a small increase in circuit scale. The problem is solved by a circuit configured using an FPGA characterized by having a majority circuit that makes a majority decision using the output of at least two circuits and one signal selected from the output of a plurality of circuits. The plurality of circuits disperse and carry out the same process, and the at least two circuits select and input an input signal to the plurality of circuits, and carry out the same process. The FPGA is further characterized in that: when all inputs in the majority circuit match a prescribed time, input signals inputted to the at least two circuits that were selected are switched to other input signals; and when a discrepancy in the inputs of the majority circuit is detected, circuit configuration information for the at least two circuits or the plurality of circuits that output an output signal is reset. |
