| 摘要 |
In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region. |
| 主权项 |
1. A microelectronic package, comprising:
a package substrate having a plurality of first terminals for connection with a component external to the package, the first terminals configured to carry address information; and first and second microelectronic elements each having a face confronting a first surface of the substrate, each microelectronic element including a memory storage array, and each microelectronic element having address inputs for receipt of address information specifying locations within the memory storage array of the respective microelectronic element, the package substrate further having a plurality of address lines electrically connected with the first terminals and configured to carry address information to a first connection region on the substrate, the first connection region having a first delay from the first terminals, the address lines being configured to carry the address information beyond the first connection region at least to a second connection region on the substrate having a second delay from the first terminals, wherein the address inputs of the first microelectronic element are coupled with each of the address lines at the first connection region, and the address inputs of the second microelectronic element are connected with each of the address lines at the second connection region, wherein the second delay is greater than the first delay. |
