Hybrid ETSOI Structure to Minimize Noise Coupling from TSV

摘要

In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

主权项

1. A method for forming an electronic device, comprising the steps of:
patterning an extremely thin silicon-on-insulator (ETSOI) layer of an ETSOI wafer into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm; forming a gate electrode over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor; and forming at least one through silicon via (TSV) in the ETSOI wafer adjacent to the transistor.