发明名称 |
TECHNIQUE FOR IMPROVING THE PERFORMANCE OF A TESSELLATION PIPELINE |
摘要 |
A tessellation pipeline includes an alpha phase and a beta phase. The alpha phase includes pre-tessellation processing stages, while the beta phase includes post-tessellation processing stages. A processing unit configured to implement a processing stage in the alpha phase stores input graphics data within a buffer and then copies over that buffer with output graphics data, thereby conserving memory resources. The processing unit may also copy output graphics data directly to a level 2 (L2) cache for beta phase processing by other tessellation pipelines, thereby avoiding the need for fixed function copy-out hardware. |
申请公布号 |
US2014267319(A1) |
申请公布日期 |
2014.09.18 |
申请号 |
US201313829461 |
申请日期 |
2013.03.14 |
申请人 |
HAKURA Ziyad S.;WANG Zhenghong |
发明人 |
HAKURA Ziyad S.;WANG Zhenghong |
分类号 |
G06T1/20 |
主分类号 |
G06T1/20 |
代理机构 |
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代理人 |
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主权项 |
1. A graphics subsystem configured to implement a graphics processing pipeline that includes a first set of processing stages and a second set of processing stages, the graphics subsystem comprising:
a first processing engine configured to:
retrieve graphics object data from a first memory unit;perform a first graphics processing operation on the graphics object data at a first processing stage included in the first set of processing stages to generate processed graphics object data;determine that a second processing stage included in the first set of processing stages is the final processing stage in the first set of processing stages; andcopy the processed graphics object data to the first memory unit, wherein the processed graphics object data overwrites at least a portion of the graphics object data within the first memory unit. |
地址 |
Gilroy CA US |