发明名称
摘要 A separation circuit separates a 32-bit dividend, for example 1695, into 4-bit segments starting from the lowest bit and outputs 9 separated dividends (X0 to X8). The position of each separated dividend counted from a separated dividend having the lowest bit is called i (i=0 to 8). A first output circuit concatenates a separated dividend and 0s the number of which is equal to integer multiple of 4 bits with the 0s at the end of the separated dividend. Each calculation circuit outputs an 8-bit quotient that is obtained by dividing by 3(=2 n -1 and n=2) a numerical value created by the first output circuit. Each calculation circuit outputs from a second output circuit a first bit sequence that is the upper 4 bits of the 8-bit quotient, and a second bit sequence in which i sets of lower 4 bits of the 8-bit quotient are arranged. A quotient addition circuit outputs, as a quotient of 1695 divided by 3, the sum of values in each of which the first bit sequence is set at upper bits and the second bit sequence is set at lower bits.
申请公布号 JP5590148(B2) 申请公布日期 2014.09.17
申请号 JP20120549558 申请日期 2010.12.24
申请人 发明人
分类号 G06F7/535 主分类号 G06F7/535
代理机构 代理人
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