| 摘要 |
The present invention relates to an eFuse OTP memory device. To achieve this, the eFuse OTP memory device includes: a control logic unit which supplies control signals for a read mode, a program mode, and a program-verify-read mode; a program column selecting unit which selects columns programmed in the program mode; a data latch unit which stores program data in the columns selected by the program column selecting unit; an OTP cell array which includes a plurality of different paired eFuse cells to perform an operation of programming eFuse or reading data; a data output buffer unit which reads data from the OTP cell array and stores the data; a comparing unit which compares the program data stored in the data latch unit with the read data stored in the data output buffer unit when the program-verify-read mode is executed; and a pass fail bar (PFb) pin which outputs the comparison result obtained in the comparing unit. The eFuse OTP memory device further comprises a variable pull-up load circuit for a sensing margin test to vary the impedance of a pull-up load of a bit line precharge circuit used in the program-verify-read mode and read mode. According to the present invention, it is possible to identify a programmed state of the eFuse OTP device while the eFuse OTP device is packaged, and prevents a sensing failure even when a link resistance to the programmed eFuse OTP device is decreased. |
