Method to improve charge trap flash memory core cell performance and reliability

摘要

A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

主权项

1. A method comprising:
disposing a tunneling dielectric layer on a substrate; disposing a charge trapping layer on the tunneling dielectric layer; patterning a plurality of trench isolation regions through the tunneling dielectric layer, and the charge trapping layer, wherein each trench isolation region includes mesas having sidewalls and tops; disposing a silicon-nitride (SiN) layer over the charge trapping layer and exposed mesas; oxidizing a portion of the SiN layer to form a blocking dielectric layer on the charge trapping layer; and disposing a polysilicon region on the blocking dielectric layer.