APPARATUS AND METHOD FOR REDUCING SAMPLING CIRCUIT TIMING MISMATCH

摘要

An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels.

主权项

1. A circuit for generating a plurality of sampling clocks synchronized relative to one another to reduce timing mismatch for sampling of multiple analog signal channels, the circuit comprising:
first circuitry configured to receive a plurality of input signals and selectively set each sampling clock of the plurality of sampling clocks to a first output state, wherein a selected sampling clock of the plurality of sampling clocks is set to the first output state when a selected input of the plurality of input signals is set to a first input state; and second circuitry configured to receive an input clock signal and transition each of the plurality of sampling clocks to a second output state through a common path, wherein the selected sampling clock is transitioned from the first output state to the second output state through the common path in response to a transition of the input clock signal from a first clock state to a second clock state.