Technique For Sub-Microsecond Latency Measurement Across A Bus

摘要

Methods and systems for determining latency across a bus, such as a PCIe bus, coupling a field programmable gate array (FPGA) and a processor having different time incrementation rates. Both the FPGA and the processor count clock ticks independently, and using a calibration offset and the two incrementation rates, the processor converts the FPGA clock ticks into processor clock ticks in order to determine latency across the bus.

主权项

1. A method for determining latency across a bus coupling a field programmable gate array (FPGA) comprising a first counter having first clock ticks with a first incrementation rate, and a processor comprising a second counter having second clock ticks with a second incrementation rate, wherein said first and second incrementation rates are not equal, the method comprising the steps of:
counting, by said first counter, a plurality of first clock ticks; counting, by said second counter, a plurality of second clock ticks; determining a calibration offset; converting, using said first and second incrementation rates and the determined calibration offset, the plurality of first clock ticks to second clock ticks.