INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL COMPARE FUNCTIONALITY

摘要

Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of the specified size in the source operand, corresponding to the mask and compare the values for equality. In some embodiments, responsive to a detection of inequality, a trap may be taken. In some alternative embodiments, a flag may be set. In other alternative embodiments, a mask field may be set to a masked state for the corresponding unequal value(s). In some embodiments, responsive to all unmasked data fields of the source operand being equal to a particular value, that value may be broadcast to all data fields of the specified size in the destination operand.

主权项

1. A processor comprising:
a vector register comprising a first plurality of data fields to store values of vector elements; a decode stage to decode a first instruction specifying: a destination operand, a size of the vector elements, a portion of the first plurality of data fields, and a source operand; and an execution unit, responsive to the decoded first instruction, to:
read values from data fields of the size of vector elements in the source operand;compare the values read from the data fields of the source operand for equality with each other; andresponsive to a detection of an inequality of one or more data fields of the source operand, signaling said detection of the inequality.