发明名称 Information processing apparatus, encoding method and frame synchronization method
摘要 Provided is an information processing apparatus including a frame generator for generating a frame by adding, to data, a header indicating a beginning position of the data, an encoder for encoding the frame generated by the frame generator according to a specific coding scheme, and generating encoded data expressed by mutually different first and second-bits, a cycle changer for changing a coding cycle in a header section by controlling the encoder, and a line coding unit for performing line coding on the encoded data generated by the encoder, and generating an encoded signal which expresses the first-bit in a form of a plurality of first levels and the second-bit in a form of a plurality of second levels different from the first levels such that a same level does not occur consecutively and for which a polarity of the level is inverted every half cycle of a clock.
申请公布号 US8831112(B2) 申请公布日期 2014.09.09
申请号 US201012778572 申请日期 2010.05.12
申请人 Sony Corporation 发明人 Maeda Takeshi
分类号 H04B5/00 主分类号 H04B5/00
代理机构 Sony Corporation 代理人 Sony Corporation
主权项 1. An information processing apparatus comprising: a line coding unit for generating encoded data, wherein the line coding unit comprises a frame generation unit and an encoder, wherein the frame generation unit generates a transmission frame by adding, to transmission data, a header indicating a beginning position of the transmission data, wherein the encoder encodes the transmission frame generated by the frame generation unit according to a specific coding scheme, and generates the encoded data expressed by mutually different first and second bit values, wherein the encoder comprises a cycle switching unit for changing a coding cycle in a header section by controlling the encoder, and wherein the first bit value is expressed in a form of a plurality of first amplitude levels and the second bit value is expressed in a form of a plurality of second amplitude levels different from the first amplitude levels, wherein the polarities of the first and second amplitude levels are inverted every half cycle of a clock.
地址 Tokyo JP