MULTI-DIE MEMORY DEVICE

摘要

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

主权项

1. A memory comprising:
a logic die including first and second memory interface circuits; a first memory die stacked with the logic die, the first memory die including first and second memory arrays, the first memory array coupled to the first memory interface circuit, the second memory array coupled to the second interface circuit; a second memory die stacked with the logic die and the first memory die, the second memory die including third and fourth memory arrays, the third memory array coupled to the first memory interface circuit, the fourth memory array coupled to the second memory interface circuit; and wherein accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.