Analog Memories Utilizing Ferroelectric Capacitors

摘要

A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.

主权项

1. A memory circuit comprising
a ferroelectric capacitor characterized by a stored charge that is stored in said ferroelectric capacitor when said ferroelectric capacitor is not powered, said stored charge representing a stored data value a reset circuit that causes said stored charge to be equal to a predetermined stored charge; a write circuit that receives a plurality of input data values, converts each of said plurality of input data values to a corresponding charge and causes said corresponding charges to be added to said stored charge; and a read circuit that determines said stored charge and generates a sum data value indicative of a sum of said plurality of input data values.