发明名称 |
Grid refinement method |
摘要 |
The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments. |
申请公布号 |
US8822106(B2) |
申请公布日期 |
2014.09.02 |
申请号 |
US201213722266 |
申请日期 |
2012.12.20 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Wang Wen-Chuan;Lin Shy-Jay;Liu Pei-Yi;Shin Jaw-Jung;Lin Burn Jeng |
分类号 |
G03F1/20;G03F7/20 |
主分类号 |
G03F1/20 |
代理机构 |
Haynes and Boone, LLP |
代理人 |
Haynes and Boone, LLP |
主权项 |
1. A method for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1, comprising:
providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments. |
地址 |
Hsin-Chu TW |