Reducing design verification time while maximizing system functional coverage

摘要

A system for functional verification of a chip design includes the chip design, a test generator, a test bench, a verification tool, and a coverage tool. The coverage tool is configured to receive chip design, user input, and coverage files from the verification tool to generate information for the test generator to improve the test coverage of the verification tool. The method includes receiving a chip design, functionally testing the chip design, generating coverage files, receiving user options, including a coverage basis, a report basis, and a defined coverage, calculating coverage impact and new overall coverage using the defined coverage and coverage files, and ranking each report basis according to coverage impact of each coverage basis.

主权项

1. A method for verifying a functionality of a chip design, the method performed by at least one processor and comprising:
(a) receiving a chip design having a plurality of design blocks; (b) functionally testing the plurality of design blocks on a test bench using a verification tool; (c) receiving coverage files corresponding to the plurality of design blocks from the verification tool; (d) receiving a design exclusion list, a coverage basis and a defined coverage; (e) for the coverage basis and each of non-excluded design blocks in the plurality of design blocks but not in the design exclusion list, calculating coverage impact and new overall coverage using the defined coverage and the coverage files; (f) ranking each of the non-excluded design blocks according to the calculated coverage impact and new overall coverage; and (g) generating a ranked candidate list based on said ranking.