发明名称 |
Routing centric design closure |
摘要 |
Method of placing and routing circuit components including: dividing a layout area of an integrated circuit (IC) design into an array of tiles, each tile having a plurality of edges that are common to adjoining tiles; placing of circuit components into the layout area of the IC design such that each tile including a plurality of circuit components, the placing of circuit components being performed for primarily routability without resort to a timing model, routability being measured by congestion of wiring nets at the tile edges; performing a virtual timing operation of the IC design with a virtual timing model assuming ideal buffering is done to test the placement of circuit components; performing a wire synthesis operation of the IC design for layer assignment, buffering and timing optimization while minimizing degradation in routability; and performing a plurality of timing optimizations of the IC design while minimizing degradation in routability. |
申请公布号 |
US8826215(B1) |
申请公布日期 |
2014.09.02 |
申请号 |
US201313902751 |
申请日期 |
2013.05.24 |
申请人 |
International Business Machines Corporation |
发明人 |
Alpert Charles J.;Li Zhuo;Nam Gi-Joon;Sze Chin Ngai;Villarrubia Paul G. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
Law Offices of Ira D. Blecker, P.C. |
代理人 |
Law Offices of Ira D. Blecker, P.C. |
主权项 |
1. A method of placing and routing circuit components comprising:
dividing a layout area of an integrated circuit (IC) design into an array of tiles, each tile having a plurality of edges that are common to adjoining tiles; placing of circuit components into the layout area of the IC design such that each tile including a plurality of circuit components, the placing of circuit components being performed for primarily routability without resort to a timing model, routability being measured by congestion of wiring nets at the tile edges; performing a virtual timing operation of the IC design with a virtual timing model assuming ideal buffering is done to test the placement of circuit components; performing a wire synthesis operation of the IC design for layer assignment, buffering and timing optimization while minimizing degradation in routability; and performing a plurality of timing optimizations of the IC design while minimizing degradation in routability; moving circuit components during the plurality of timing optimizations such that a disruptiveness of moving circuit components varies from more disruptive in early timing optimizations to less disruptive in later timing optimizations; wherein the placing of circuit components starts good routability and the following timing optimization steps maintain the good routability; and wherein the method is performed by one or more computing devices. |
地址 |
Armonk NY US |