METHOD AND ARRANGEMENT FOR GENERATING A CLOCK SIGNAL BY MEANS OF A PHASE LOCKED LOOP

摘要

A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.

主权项

1. A method for generating a clock signal by a phase locked loop, in which a divided clock signal generated from the clock signal is compared with a reference clock, and a frequency and a phase angle of the clock signal to be generated is set as a function of said comparison, comprising: generating a plurality of selection signals respectively shifted by a time difference delta t from the divided clock signal, generating a comparison signal under control by an edge of the reference clock, and starting a comparison in the case that what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and outputting said selected selection signal.