INTEGRATED CIRCUIT INTERCONNECTS AND METHODS OF MAKING SAME

摘要

A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is etched back a predetermined thickness from the top of the dielectric layer to expose the inside sidewalls thereof. A sidewall barrier layer is formed on the sidewalls of the dielectric layer. A copper-containing layer is formed over the metal layer, the dielectric layer, and the sidewall barrier layers. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately the juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer.

主权项

1. A method for forming a semiconductor interconnect structure, comprising:
forming a dielectric layer on a substrate; patterning the dielectric layer to form an opening in the dielectric layer; filling the opening and covering the dielectric layer with a metal layer; planarizing the metal layer so that the metal layer is co-planar with a top of the dielectric layer; etching back the metal layer a predetermined thickness from the top of the dielectric layer to expose inside sidewalls of the dielectric layer; forming a sidewall barrier layer on the sidewalls of the dielectric layer, the sidewall barrier layer having a predetermined thickness; forming a copper-containing layer over the metal layer, the dielectric layer, and the sidewall barrier layers; and etching the copper-containing layer to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately a juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer.