NAND FLASH MEMORY UNIT AND NAND FLASH MEMORY ARRAY

摘要

A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.

主权项

1. A NAND flash memory unit, comprising:
a string of memory cells connected in series; two source/drain (S/D) regions coupled to two terminals of the string of memory cells; at least one select transistor coupled between a terminal of the string and an S/D region, for selecting the string of memory cells; and at least one erase transistor coupled between the at least one select transistor and the one of the two S/D regions, wherein a voltage VCG is applied to gates of the memory cells, a voltage VS/D positively higher than the voltage VCG is applied to the S/D regions, a voltage VSG satisfying an inequality of “VSG