FLASH MEMORY DEVICE REDUCING LAYOUT AREA

摘要

Disclosed is a flash memory device capable of reducing a layout area. In the flash memory device according to one embodiment of the present invention, odd power transistors and even power transistors of a plurality of power connection units corresponding to a plurality of bit line pairs and even selective transistors and odd selective transistors of a plurality of selective connection units are arranged in one common active region. According to the flash memory device of the present invention, a layout length of a vertical direction is reduced because the number of separation oxide layers for distinguishing the active region and the number of layout regions for the same is reduced, and thereby the entire layout area is remarkably reduced.