Metal gate structures for CMOS transistor devices having reduced parasitic capacitance

摘要

A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.

主权项

1. A field effect transistor (FET) device, comprising:
a gate structure formed over a substrate, the gate structure comprising a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material disposed above a topmost surface of the substrate and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also comprising a metal material having a second width smaller than the first width; the gate structure further comprising a wide top portion formed on top of the narrow portion, the wide top portion comprising a metal material having a third width that is greater than the second width; sidewall spacers formed in contact with a top surface of the substrate and disposed adjacent outer edges of the wide bottom portion of the gate structure, wherein the wide top portion is disposed above a top of the sidewall spacers; and a dielectric layer disposed between and in contact with the wide bottom portion and the wide top portion, the dielectric layer also disposed between and in contact with the narrow portion and the sidewall spacers.