发明名称 |
LOOK-UP BASED FAST LOGIC SYNTHESIS |
摘要 |
Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells. |
申请公布号 |
US2014237437(A1) |
申请公布日期 |
2014.08.21 |
申请号 |
US201314068253 |
申请日期 |
2013.10.31 |
申请人 |
Synopsys, Inc. |
发明人 |
Mang Yiu-Chung;Dhar Sanjay;Khandelwal Vishal;Lee Kok Kiong |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A method for performing circuit synthesis, the method comprising:
receiving a cell in a circuit design that is to be optimized; performing, by a computer, a table lookup operation on one or more tables based on information associated with the cell to obtain a set of optimal cell configurations, wherein the one or more tables enable the set of optimal cell configurations to be looked up based on the information associated with the cell; and replacing the cell in the circuit design with a cell configuration selected from the set of optimal cell configurations. |
地址 |
Mountain View CA US |