| 摘要 |
Circuit apparatus and method for reading a data value stored in a memory cell (10, fig 7) of a memory unit, the memory unit comprising a plurality of memory cells (which may be Static RAM or SRAM cells) in which access to each memory cell is controlled by a combination of both a word line WL, 27, 28 and a pair of bit lines BLA, BLB 11, 12 associated with the memory cell 20. MOSFET devices 13a, 13b have their gates connected directly to one of the complimentary bit lines, BLB and BLA respectively. The method comprises driving a voltage on the word line associated with the memory cell high, applying a current to charge the pair of bit lines associated with the memory cell, removing the current from the pair of bit lines associated with the memory cell, and sensing a voltage difference between the pair of bit lines associated with the memory cell to determine the data value (figure 8). The memory unit may also comprise a plurality of memory cells groups (40 figure 10) comprising a plurality of memory cells (20, figure 10) that are each operatively connected to a first and second local bit line (40a, 40b fig 10), each cell associated with word line access devices (26a, 26b) , the first and second local bit lines connected to first and second column bit lines (11, 12 figure 10) by means of access devices (13a, 13b fig 10) which are directly enabled by the column bit lines. The access devices may be MOSFET devices (13a, 13b) and may have their gates directly connected to one of the complementary column bit lines BLA, BLB. |
