发明名称 MEMORY INTERFACE
摘要 The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.
申请公布号 EP2686774(A4) 申请公布日期 2014.08.20
申请号 EP20110860733 申请日期 2011.03.14
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 UDIPI, ANIRUDDHA NAGENDRAN;MURALIMANOHAR, NAVEEN;JOUPPI, NORMAN PAUL;BALASUBRAMONIAN, RAJEEV;DAVIS, ALAN LYNN
分类号 G06F13/16;G06F12/00 主分类号 G06F13/16
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