Shift register unit, shift register, display panel and display

摘要

The disclosure discloses a shift register unit, a shift register, a display panel and a display, and belongs to display driving technology. The shift register unit comprises: twelve transistors M1, M2, . . . , M12; one capacitor C1; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one or more power supply terminals. The disclosure may decrease the output delay and attenuation, and improve an anti-interference capability, so that the shift register may operate stably and a driving margin of the shift register could be increased.

主权项

1. A shift register unit, comprising: twelve transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and, M12; one capacitor C1; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one power supply terminal VSS, and connection relationships among them are as follows:
a gate of the M1 is connected to both the signal input terminal INPUT and gates of the M6 and M9, and a source of the M1 is connected to drains of the M2 and M11; a gate of the M2 is connected to the signal input terminal RESET; both a gate and a drain of the M5 are connected to the signal input terminal CLKB, and a source of the M5 is connected to drains of the M6 and M7; a gate of the M8 is connected to the source of the M5, a drain of the M8 is connected to both drains of the M9 and M10 and gates of the M11 and M12; a drain of the M3 is connected to the signal input terminal CLK, a gate of the M3 is connected to one end of the capacitor C1 and the source of the M1, and a source of the M3 is connected to the other end of the capacitor C1, gates of the M7 and M10, drains of the M12 and M4 and the signal output terminal OUTPUT; sources of M2, M11, M6, M7, M9, M10, M12 and M4 are connected to the power supply terminal VSS, and a gate of the M4 is connected to the signal input terminal RESET; said shift register unit further comprises two additional signal input terminals: fifth signal input terminal and sixth signal input terminal, a drain of the M1 is connected to the fifth signal input terminal, and when the gate of the M1 is at the high level, the signal input terminal at the drain of the M1 is also at a high level; a source of the M8 is connected to the sixth signal input terminal, and when the gate of the M8 is at the high level, the signal input terminal at the source of the M8 is also at a high level.